Data Storage Device

ABSTRACT

Optimized writing techniques for nonvolatile memory are presented. A microcontroller switches between a first writing mode and a second writing mode to write data to the nonvolatile memory. The switching between the first writing mode and the second writing mode depends on a first accumulated amount of data written to the nonvolatile memory in the first writing mode, or a number of spare blocks of the nonvolatile memory that is evaluated after a garbage collection procedure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of application Ser. No. 15/922,666 filed on Mar. 15, 2018, which claims priority of Taiwan Patent Application No. 106120335 filed on Jun. 19, 2017, the entirety of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to optimization of an operating method for nonvolatile memory.

Description of the Related Art

There are various forms of nonvolatile memory (NVM) used in data storage devices for long-term data retention, such as a flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM, spin transfer torque-RAM (STT-RAM), and so on.

The lifespan of nonvolatile memory is limited. For example, the erasure of each block of a flash memory should be limited. When the number of times that a block has been erased exceeds an upper limit, the block should be protected from being further allocated to receive write data. With the increasing number of blocks exceeding the upper limit on the number of erasures, the flash memory approaches the end of its lifespan. Since the erasing demand depends on the operating method for the flash memory, how to optimize the operation of the nonvolatile memory and then extend the life of the device is a major issue in the technical field.

BRIEF SUMMARY OF THE INVENTION

A data storage device in accordance with an exemplary embodiment of the disclosure is provided.

A data storage device in accordance with an exemplary embodiment of the disclosure has a nonvolatile memory and a microcontroller. The microcontroller writes data to the nonvolatile memory and counts a first accumulated amount of data written to the nonvolatile memory in a first writing mode. When a condition is satisfied by the first accumulated amount of data, the microcontroller switches to write data to the nonvolatile memory in a second writing mode. When the condition is not satisfied by the first accumulated amount of data, the microcontroller keeps using the first writing mode to write data to the nonvolatile memory in the first writing mode.

The microcontroller may further count a second accumulated amount of data written to the nonvolatile memory in the second writing mode. The condition is judged based on the first accumulated amount of data and the second accumulated amount of data.

In an exemplary embodiment, data is stored to single level cells when the first writing mode is adopted, and is stored to multiple level cells (dual or triple or more) when the second writing mode is adopted.

In another exemplary embodiment, the microcontroller evaluates a number of spare blocks of the nonvolatile memory after a garbage collection procedure. When a condition is satisfied by the number of spare blocks, the microcontroller uses a first writing mode to write data to the nonvolatile memory. When the condition is not satisfied by the number of spare blocks, the microcontroller uses a second writing mode to write data to the nonvolatile memory. The condition may be judged based on the number of spare blocks and a threshold value.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIGS. 1A and 1B illustrate the distribution probability of storage cells for SLC and TLC techniques, respectively, with the logical meanings changed by modifying the floating gate electrons;

FIG. 2 is a block diagram depicting a data storage device 200 in accordance with an exemplary embodiment of the disclosure;

FIG. 3 is a flowchart illustrating how the microcontroller 204 operates the flash memory 202 according to the judgment formulas (1) and (2); and

FIG. 4 depicts a performance diagram based on the aforementioned judgment formulas (1) and (2) with a horizontal axis showing an accumulated amount of writing data and a vertical axis showing the performance of data storage device 200.

DETAILED DESCRIPTION OF THE INVENTION

The following description shows exemplary embodiments of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

A nonvolatile memory may be a memory device for long-term data retention such as a flash memory, a magnetoresistive RAM, a ferroelectric RAM, a resistive RAM, a spin transfer torque-RAM (STT-RAM) and so on. The following discussion is regarding flash memory in particular as an example, but it is not intended to limit the application to the field of flash memory.

The flash memory is often used as a storage medium in today's data storage devices, for implementations of a memory card, a USB flash device, an SSD and so on. In another exemplary embodiment, the flash memory is packaged with a controller to form a multiple-chip package and named eMMC.

A data storage device using a flash memory as a storage medium can be applied to a variety of electronic devices, including a smartphone, a wearable device, a tablet computer, a virtual reality device, etc. A central processing unit (CPU) of an electronic device may be regarded as a host operating a data storage device equipped on the electronic device.

The storage space of a flash memory may be managed in blocks. Each block can be allocated to use a specific form to store data. For example, a block allocated to provide single level cells (SLCs) to store data is called an SLC block, and a block allocated to provide triple level cells (TLCs) to store data is called a TLC block. An SLC (single level cell) stores one single bit. A TLC (triple level cell) stores three bits. In the same physical storage size, the number of data stored by SLCs is only one-third of that stored by TLCs. In addition, a TLC block can be operated in a TLC writing mode or an SLC writing mode. In SLC writing mode, a TLC block imitates an SLC block, i.e., each storage cell of the TLC block capable of storage of 3-bit data is operated to store only one bit of data (valid data). In TLC writing mode, each storage cell of the TLC block stores 3 bits of data.

FIGS. 1A and 1B illustrate the distribution probability of storage cells for SLC and TLC techniques, respectively, with the logical meanings changed by modifying the floating gate electrons. As shown, the logical definition of a storage cell is determined according to the gate floating electrons of the storage cell. The logical boundary of SLC is clearer in comparison with the logical boundaries of TLC. Single level cells (SLCs) are more reliable and allow a faster writing speed. Triple level cells (TLCs) have an advantage of storage capacity. Single level cells (SLCs) involve write amplification issues. To store the same data, a much more space is required by SLC storage in comparison with TLC storage, resulting in excessive erasure operations and shortening the lifetime of the flash memory. Considering memory capacity, the data in SLCs are moved to TLCs (e.g., by garbage collection) during the proper time, which can also result in excessive erasure operations. Considering the lifespan of flash memory, how to optimize the allocation of blocks (e.g., switching between SLC and TLC writing modes) is the focus of the following discussion.

FIG. 2 is a block diagram depicting a data storage device 200 in accordance with an exemplary embodiment of the disclosure. The data storage device 200 uses a flash memory 202 as the storage medium and has a microcontroller 204. Through the microcontroller 204, a host 206 accesses the flash memory 202. The microcontroller 204 may be loaded with code and has computing hardware that executes the code. The storage space of the flash memory 202 is managed in units of blocks as described above, and can be individually allocated to store data in an SLC or TLC writing mode. The microcontroller 204 accumulates all the accumulated amount SLC_WCnt of data that the host 206 has ever requested to write to the flash memory 202 in the SLC writing mode, and another accumulated amount TLC_WCnt of data that the host 206 has ever requested to write to the flash memory 202 in the TLC writing mode. When allocating the flash memory 202 to provide storage space, the microcontroller 204 takes the accumulated amount SLC_WCnt and the accumulated amount TLC_WCnt into account to store data in the SLC writing mode and in the TLC writing mode alternately or particularly using the SLC writing mode or particularly using the TLC writing mode to store data. In the SLC writing mode, the microcontroller 204 allocates the flash memory 202 to provide blocks working as SLCs to store write data from the host 206. In the TLC writing mode, the microcontroller 204 allocates the flash memory 202 to provide blocks working as TLCs to store write data from the host 206. By properly switching between SLC and TLC writing modes, the SLC write amplification with the risk of surge in erase count will be suppressed, data storage device 200 life is not threatened and the data storage device 200 can maintain a certain level of performance during the warranty period. Even if the warranty period has nearly expired, the data storage device 200 still has enough capacity to switch to a high-speed and high-reliability SLC writing mode.

In an exemplary embodiment, the following judgment formula (1) is used:

((TLC_WCnt+N)/M)<SLC_WCnt  (1)

where N and M are positive integers. The accumulated amount SLC_WCnt increases when data is written to SLC blocks. When the judgment formula (1) is true, the microcontroller 204 stops operating the flash memory 202 in the SLC writing mode and switches the flash memory 202 to the TLC writing mode. The flash memory 202 is operated in the SLC writing mode during a limited period and can be properly switched to the TLC writing mode. The flash memory 202, therefore, is not stuck in the SLC writing mode. The erase count of each block does not increase quickly due to long-term operation in the SLC writing mode.

The numerical values N and M of the judgment formula (1) may be set to meet the warranty requirements of the data storage device 200 and depend on the physical characteristics of the flash memory 202. In an exemplary embodiment of the data storage device 200, the amount of write data in warranty is 72T, the flash memory 202 has 900 blocks, each block is capable of storing 144M data, and the upper limit for erasure of each block is 1500 times. For each block, 583 incidents (72T/(900*144M)) of erasure may happen for the guaranteed 72T write data of the data storage device 200. Considering the upper limit, 1500 times, of the erasure of each block, there are 916 erase counts left for each block to be spent on SLC writing mode. In the judgment formula (1), N may be 12T and M may be 12, so that the 916 incidents of SLC block erasure can happen evenly over the life cycle of the flash memory 202. In another exemplary embodiment, considering the SLC write amplification phenomenon, 1166 incidents (583*2) of erasure of each block may be spent on the guaranteed amount of write data. Less erasure can be spent on additional data storage. The numerical values N and M in the judgment formula (1) can also have a corresponding design.

In another exemplary embodiment, the following judgment formula (2) is used:

SpareBlk_Num>SLC_Th  (2)

SpareBlk_Num is the total number of spare blocks in the flash memory 202. SLC_Th is a threshold for switching the flash memory 202 to the SLC writing mode. When allocating the flash memory 202 to provide space to store data from the host 206, the microcontroller 204 checks the judgment formula (2). If satisfied, the spare block within the flash memory 202 is sufficient, not necessary to pursue storage density. The microcontroller 204 operates the flash memory 202 in the SLC writing mode, making good use of the high reliability and high write performance of SLC writing mode. The judgment formula (2) shows a condition to be satisfied to switch the flash memory to SLC writing mode.

In an exemplary embodiment, when no read or write requests are issued from the host 206 to the flash memory 202 or when the system is idle, the microcontroller 204 moves the data written to the flash memory in the SLC writing mode to TLC blocks and thereby the data density is improved. The aforementioned data movement increases the number of spare blocks, facilitating the judgment of the judgment formula (1) being true.

FIG. 3 is a flowchart illustrating how the microcontroller 204 operates the flash memory 202 according to the judgment formulas (1) and (2). In step S302, the microcontroller 204 receives a write request from the host 206. In step S304, the microcontroller 204 checks the judgment formula (2). When the judgment formula (2) is not true, the flash memory 202 is not rich in space and the microcontroller 204 allocates the blocks as TLC blocks to store data from the host 206 by the TLC writing mode according to step S306. When the judgment formula (2) is true, the flash memory 202 is rich in space and the microcontroller 204 further checks the judgment formula (1). When the accumulated amount SLC_WCnt of data written to the nonvolatile memory in the SLC writing mode is not large enough to make the judgment formula (1) true, step S310 is performed and the microcontroller 204 allocates blocks to store the data from the host 206 in the SLC writing mode to make good use of the high reliability and high writing speed of SLC writing.

FIG. 4 depicts a performance diagram based on the aforementioned judgment formulas (1) and (2) with a horizontal axis showing an accumulated amount of writing data and a vertical axis showing the performance of data storage device 200. The SLC writing mode is applied in an interleaving way. There is still a chance to store data in the SLC writing mode even when approaching the end of the lifespan (e.g., after nearly 72T data writing) of the data storage device 200. As shown in this performance diagram, data is written by the SLC writing mode and TLC writing mode alternately. Considering the actual operations of the data storage device 200, the 1T SLC writing may be more finely divided and spread over the 13T writing period (which includes 1T SLC writing and 12T TLC writing).

A special operation of the data storage device 200 is discussed in this paragraph. Only a small amount of data is written to the flash memory 202 and data at a particular logical address is repeatedly updated. Due to the judgment formula (1), the flash memory 202 does not fully use the SLC writing mode to receive data from the host 206 although the storage space of the flash memory 202 is quite sufficient. The flash memory 202, therefore, is protected from premature damage due to write amplification of SLC writing technology.

Another special operation of the data storage device 200 is discussed in this paragraph. The host 206 requests to write a large amount of data. Due to the judgment formula (1), the flash memory 202 does not fully use the SLC writing mode at the beginning of the large data writing. The judgment formula (2) may be kept satisfied for a period of time. Although a considerable amount of data has to be written to the flash memory 202, the data storage device 200 still has a chance to store the write data in SLC writing mode after a period of data writing, benefited by the high reliability and the high write speed of the SLC writing mode.

In another exemplary embodiment, the judgment formula (1) to be checked for switching from the SLC writing mode to the TLC writing mode may be slightly modified. The ratio of the accumulated amount SLC_WCnt and the accumulated amount TLC_WCnt can be controlled by other judgments. In an exemplary embodiment, it is determined whether the accumulated amount SLC_WCnt exceeds a dynamic criterion (dynamic threshold value). This dynamic criterion varies with the accumulated amount TLC_WCnt. When the accumulated amount SLC_WCnt exceeds the dynamic criterion, the microcontroller 204 switches the SLC writing mode to the TLC writing mode to allocate the blocks in a proper way for storing write data requested by the host 206.

In another exemplary embodiment, the microcontroller 204 operates the flash memory 202 to switch between the SLC writing mode and another writing mode that uses one storage cell to store more or less bits of data. For example, one storage cell of the flash memory 202 may be allocated to store two bits and is called a multiple level cell (MLC). The microcontroller 204 may operate the flash memory 202 to switch between an SLC writing mode and an MLC writing mode. In another exemplary embodiment, the microcontroller 204 may operate the flash memory 202 to switch among three or more kinds of writing modes. The microcontroller 204 may operate the flash memory 202 to switch among an SLC writing mode, an MLC writing mode and a TLC writing mode. In addition, as technology evolves, the technology of storing more bits of data in a single storage cell can also be applied to the present case. The MLC and TLC techniques described above can also be replaced by other numerical multi-level cell techniques.

Other techniques that use the aforementioned concepts to operate a nonvolatile memory are within the scope of the disclosure. Based on the above contents, the present invention further relates to methods for operating a nonvolatile memory.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. 

What is claimed is:
 1. A data storage device, comprising: a nonvolatile memory; and a microcontroller, writing data to the nonvolatile memory and counting a first accumulated amount of data written to the nonvolatile memory in a first writing mode, wherein: when a condition is satisfied by the first accumulated amount of data, the microcontroller switches to write data to the nonvolatile memory in a second writing mode; and when the condition is not satisfied by the first accumulated amount of data, the microcontroller keeps using the first writing mode to write data to the nonvolatile memory in the first writing mode.
 2. The data storage device as claimed in claim 1, wherein the nonvolatile memory provides less data capacity when the data is written in the first writing mode than in the second writing mode.
 3. The data storage device as claimed in claim 1, wherein the data is written to the nonvolatile memory faster in the first writing mode than in the second writing mode.
 4. The data storage device as claimed in claim 1, wherein the first writing mode is a single level cell (SLC) writing mode.
 5. The data storage device as claimed in claim 1, wherein: the microcontroller further counts a second accumulated amount of data written to the nonvolatile memory in the second writing mode; the condition is judged based on the first accumulated amount of data and the second accumulated amount of data.
 6. A data storage device, comprising: a nonvolatile memory; and a microcontroller, controlling the nonvolatile memory, wherein the microcontroller evaluates a number of spare blocks of the nonvolatile memory after a garbage collection procedure, wherein: when a condition is satisfied by the number of spare blocks, the microcontroller uses a first writing mode to write data to the nonvolatile memory; and when the condition is not satisfied by the number of spare blocks, the microcontroller uses a second writing mode to write data to the nonvolatile memory.
 7. The data storage device as claimed in claim 6, wherein the nonvolatile memory provides less data capacity when the data is written in the first writing mode than in the second writing mode.
 8. The data storage device as claimed in claim 6, wherein the data is written to the nonvolatile memory faster in the first writing mode than in the second writing mode.
 9. The data storage device as claimed in claim 6, wherein the first writing mode is a single level cell (SLC) writing mode.
 10. The data storage device as claimed in claim 6, wherein the condition is judged based on the number of spare blocks and a threshold value. 